DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, Gyeongcheol | ko |
dc.contributor.author | Kim, Junsoo | ko |
dc.contributor.author | Kim, Joo-Young | ko |
dc.date.accessioned | 2022-10-17T07:01:41Z | - |
dc.date.available | 2022-10-17T07:01:41Z | - |
dc.date.created | 2022-10-17 | - |
dc.date.created | 2022-10-17 | - |
dc.date.issued | 2022-07 | - |
dc.identifier.citation | IEEE COMPUTER ARCHITECTURE LETTERS, v.21, no.2, pp.101 - 104 | - |
dc.identifier.issn | 1556-6056 | - |
dc.identifier.uri | http://hdl.handle.net/10203/298970 | - |
dc.description.abstract | FPGA is a promising platform in designing hardware due to its design flexibility and fast development cycle, despite the device's limited hardware resources. To address this, latest FPGAs have adopted a multi-die architecture that employs multiple dies in a single device to provide abundant hardware resources. However, the multi-die architecture causes critical timing issues when signal paths cross the die-to-die boundaries, adding another design challenge in using FPGA. We propose OpenMDS, an open-source shell generation framework for high-performance design on Xilinx multi-die FPGAs. Based on the user's design requirements, it generates an optimized shell for the target FPGA via die-level kernel encapsulation, automated bus pipelining, and customized floorplanning. To evaluate our shell generation, we compare its implementation results against Xilinx's Vitis framework. As a result, OpenMDS uses average 20% less logic resources than Vitis for the same shell functionality. To show its practicality, we use OpenMDS for the design of machine learning accelerator that contains multiple systolic-array processors. OpenMDS achieves 247MHz and 235MHz kernel frequency and 400MHz and 429MHz memory bus frequency for U50 and U280, respectively, for the accelerator design over 90% logic utilization, claiming up to 12.27% and 22.92% higher kernel and memory bus frequency over Vitis. | - |
dc.language | English | - |
dc.publisher | IEEE COMPUTER SOC | - |
dc.title | OpenMDS: An Open-Source Shell Generation Framework for High-Performance Design on Xilinx Multi-Die FPGAs | - |
dc.type | Article | - |
dc.identifier.wosid | 000861415100001 | - |
dc.identifier.scopusid | 2-s2.0-85137563754 | - |
dc.type.rims | ART | - |
dc.citation.volume | 21 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 101 | - |
dc.citation.endingpage | 104 | - |
dc.citation.publicationname | IEEE COMPUTER ARCHITECTURE LETTERS | - |
dc.identifier.doi | 10.1109/LCA.2022.3202016 | - |
dc.contributor.localauthor | Kim, Joo-Young | - |
dc.contributor.nonIdAuthor | Shin, Gyeongcheol | - |
dc.contributor.nonIdAuthor | Kim, Junsoo | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Field programmable gate arrays | - |
dc.subject.keywordAuthor | Kernel | - |
dc.subject.keywordAuthor | Hardware | - |
dc.subject.keywordAuthor | Pipeline processing | - |
dc.subject.keywordAuthor | Timing | - |
dc.subject.keywordAuthor | Routing | - |
dc.subject.keywordAuthor | Registers | - |
dc.subject.keywordAuthor | FPGA | - |
dc.subject.keywordAuthor | shell | - |
dc.subject.keywordAuthor | design automation | - |
dc.subject.keywordAuthor | open-source | - |
dc.subject.keywordAuthor | high-performance design | - |
dc.subject.keywordAuthor | multi-die FPGA | - |
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