An Overturned Charge Injection Synaptic Transistor with a Floating-gate for Neuromorphic Hardware Computing

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dc.contributor.authorKim, Myung-Suko
dc.contributor.authorKim, Jin-Kiko
dc.contributor.authorYun, Gyeong-Junko
dc.contributor.authorYu, Ji-Manko
dc.contributor.authorHan, Joon-Kyuko
dc.contributor.authorLee, Jung-Wooko
dc.contributor.authorSeo, Seokhoko
dc.contributor.authorChoi, Shinhyunko
dc.contributor.authorChoi, Yang-Kyuko
dc.date.accessioned2022-09-13T02:00:32Z-
dc.date.available2022-09-13T02:00:32Z-
dc.date.created2022-08-01-
dc.date.created2022-08-01-
dc.date.issued2022-09-
dc.identifier.citationIEEE ELECTRON DEVICE LETTERS, v.43, no.9, pp.1440 - 1443-
dc.identifier.issn0741-3106-
dc.identifier.urihttp://hdl.handle.net/10203/298479-
dc.description.abstractAn overturned charge injection synaptic transistor (OCIST) is experimentally demonstrated for neuromorphic hardware computing. The structure of the OCIST is similar to that of a conventional floating gate memory except for the directionality of charge injection. The charge valve layer (CVL) of the OCIST is analogous to a blocking oxide of a floating gate memory device. The OCIST employs the CVL to control charge flow to the floating gate, while the floating gate memory utilizes a tunneling oxide as a gate oxide for this. Because the CVL and the gate oxide are decoupled in the OCIST, the CVL is independently engineerable without any sacrifice of the gate oxide quality and scalability. Moreover, the selection spectrum for the CVL material is wide. Linearity and symmetry of synaptic potentiation and depression were improved. In addition, a classification accuracy of 92.4% for handwritten digits in the MNIST dataset was achieved.-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleAn Overturned Charge Injection Synaptic Transistor with a Floating-gate for Neuromorphic Hardware Computing-
dc.typeArticle-
dc.identifier.wosid000845067200016-
dc.identifier.scopusid2-s2.0-85135743824-
dc.type.rimsART-
dc.citation.volume43-
dc.citation.issue9-
dc.citation.beginningpage1440-
dc.citation.endingpage1443-
dc.citation.publicationnameIEEE ELECTRON DEVICE LETTERS-
dc.identifier.doi10.1109/LED.2022.3194556-
dc.contributor.localauthorChoi, Shinhyun-
dc.contributor.localauthorChoi, Yang-Kyu-
dc.contributor.nonIdAuthorYun, Gyeong-Jun-
dc.contributor.nonIdAuthorSeo, Seokho-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorNonvolatile memory-
dc.subject.keywordAuthorLogic gates-
dc.subject.keywordAuthorSynapses-
dc.subject.keywordAuthorLinearity-
dc.subject.keywordAuthorSilicon-
dc.subject.keywordAuthorDepression-
dc.subject.keywordAuthorTransistors-
dc.subject.keywordAuthorCharge valve layer-
dc.subject.keywordAuthorfloating gate-
dc.subject.keywordAuthorneuromorphic-
dc.subject.keywordAuthorpotentiation and depression-
dc.subject.keywordAuthoroverturned charge injection synaptic transistor (OCIST)-
dc.subject.keywordAuthorsynapse-
dc.subject.keywordPlusSILICON-NITRIDE-
dc.subject.keywordPlusDEVICES-
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