DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, Suneui | ko |
dc.contributor.author | Choi, Seojin | ko |
dc.contributor.author | Yoo, Seyeon | ko |
dc.contributor.author | Cho, Yoonseo | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2022-09-06T05:01:13Z | - |
dc.date.available | 2022-09-06T05:01:13Z | - |
dc.date.created | 2021-11-24 | - |
dc.date.created | 2021-11-24 | - |
dc.date.issued | 2022-09 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.57, no.9, pp.2829 - 2840 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/298379 | - |
dc.description.abstract | multiplier (PG-ILFM)-based phase detector (PD) that can maintain a high phase-error-detection gain even at high frequencies above 100 GHz, this W-band PLL can achieve a very low in-band phase noise. Due to this intrinsically low in-band phase noise, the bandwidth of the PLL can be extended so that it can suppress the poor phase noise of the W-band voltage-controlled oscillator (VCO). The frequency-offset canceller (FOC) is also presented to remove the possible frequency offset between the main VCO of the PLL and the replica VCO of the PG-ILFM-based PD. Operating in the background, the FOC can ensure high phase-error-detection gain and wide loop bandwidth and, thus, the low-jitter performance of the PLL. The proposed PLL was fabricated in a 65-nm CMOS process, and it used a power of 22.5 mW and an area of 0.16 mm². The rms jitter, integrated from 1 kHz to 300 MHz, was 82 fs at 102 GHz. It also achieved the FoMJIT of -248.2 dB, which is the best among the state-of-the-art W-band frequency synthesizers. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector | - |
dc.type | Article | - |
dc.identifier.wosid | 000732072300001 | - |
dc.identifier.scopusid | 2-s2.0-85118634796 | - |
dc.type.rims | ART | - |
dc.citation.volume | 57 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 2829 | - |
dc.citation.endingpage | 2840 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/jssc.2021.3123156 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Choi, Seojin | - |
dc.contributor.nonIdAuthor | Yoo, Seyeon | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Voltage-controlled oscillators | - |
dc.subject.keywordAuthor | Phase locked loops | - |
dc.subject.keywordAuthor | Jitter | - |
dc.subject.keywordAuthor | Phase noise | - |
dc.subject.keywordAuthor | Phase frequency detectors | - |
dc.subject.keywordAuthor | Bandwidth | - |
dc.subject.keywordAuthor | Detectors | - |
dc.subject.keywordAuthor | 6G | - |
dc.subject.keywordAuthor | beyond 5G | - |
dc.subject.keywordAuthor | detection gain | - |
dc.subject.keywordAuthor | injection locked | - |
dc.subject.keywordAuthor | jitter | - |
dc.subject.keywordAuthor | phase noise | - |
dc.subject.keywordAuthor | phase-locked loop (PLL) | - |
dc.subject.keywordAuthor | power gating | - |
dc.subject.keywordAuthor | sampling | - |
dc.subject.keywordAuthor | W-band | - |
dc.subject.keywordPlus | SUB-SAMPLING PLL | - |
dc.subject.keywordPlus | TRACKING LOOP | - |
dc.subject.keywordPlus | TUNING RANGE | - |
dc.subject.keywordPlus | LC-VCO | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | SYNTHESIZER | - |
dc.subject.keywordPlus | ARCHITECTURE | - |
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