A Junctionless Single Transistor Neuron with Vertically Stacked Multiple Nanowires for Highly Scalable Neuromorphic Hardware

Abstract

A junctionless single-transistor neuron (JT-neuron) composed of vertically stacked multiple nanowires (NWs) with a gate-all-around structure (GAA) is demonstrated to drive more synapses compared with a single NW junctionless GAA MOSFET for neuromorphic hardware. A homogeneously doped junctionless structure is advantageous for fabrication simplicity compared with a heterogeneously doped junction structure, which has been widely used as an inversion mode transistor. The nature of the junctionless MOSFET is robust to punchthrough or drain-induced barrier lowering (DIBL) in a scaled transistor. Furthermore, vertically stacked multiple NWs are favorable for improving the on-state current to be able to derive more synapses and higher packing density without sacrifice of the footprint area compared with a laterally deployed NW structure. To evaluate the feasibility of applying the JT-neuron to a spiking neural network (SNN), experimental-based simulations are performed. A recognition accuracy of 91.7% is achieved for Modified National Institute of Standards and Technology (MNIST) handwritten digits.