DC Field | Value | Language |
---|---|---|
dc.contributor.author | Hwang, Junghyeon | ko |
dc.contributor.author | Kim, Minki | ko |
dc.contributor.author | Jung, Minhyun | ko |
dc.contributor.author | Kim, Taeho | ko |
dc.contributor.author | Goh, Youngin | ko |
dc.contributor.author | Lee, Yongsun | ko |
dc.contributor.author | Jeon, Sanghun | ko |
dc.date.accessioned | 2022-06-07T07:00:41Z | - |
dc.date.available | 2022-06-07T07:00:41Z | - |
dc.date.created | 2022-05-16 | - |
dc.date.created | 2022-05-16 | - |
dc.date.created | 2022-05-16 | - |
dc.date.issued | 2022-06 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.69, no.6, pp.3439 - 3445 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | http://hdl.handle.net/10203/296843 | - |
dc.description.abstract | Hafnia-based ferroelectric field-effect transistors (FeFETs) with low power, scalability, and nonvolatile switching can overcome the performance limitations of conventional von Neumann computing technology. However, achieving a large memory window and excellent endurance in FeFET devices composed of two capacitors, such as ferroelectric and interfacial insulator capacitors, remains a challenge due to the strong electric field applied to the insulator, which accounts for the low permittivity (k) of interfacial insulator. In addition, write disturb (WD) is considered to be a hurdle in the practical array operation of 1T-type FeFET devices. In this study, we propose a core process in which the dielectric constant and grain size of hafnia ferroelectric are adjusted by the ramping/cooling process, achieving high speed (20 ns), high reliability (10(1)SUPERSCRIPT ZERO), and negligible disturb (0 V in 1/3 $V_{dd}$ operation) FeFET. This results from effective voltage drop and switching across a relatively low-k ferroelectric capacitor that is connected with an interfacial insulator. Intriguingly, using low-k HfZrO as a gate, the proposed 3-D structure FeFET exhibits an improved memory window and robustness in WD in the array operation. These results suggest an informative way to design a high memory performance of FeFETs for future applications. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Relatively Low-k Ferroelectric Nonvolatile Memory Using Fast Ramping Fast Cooling Annealing Process | - |
dc.type | Article | - |
dc.identifier.wosid | 000788900800001 | - |
dc.identifier.scopusid | 2-s2.0-85129620097 | - |
dc.type.rims | ART | - |
dc.citation.volume | 69 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 3439 | - |
dc.citation.endingpage | 3445 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.identifier.doi | 10.1109/TED.2022.3165167 | - |
dc.contributor.localauthor | Jeon, Sanghun | - |
dc.contributor.nonIdAuthor | Hwang, Junghyeon | - |
dc.contributor.nonIdAuthor | Kim, Minki | - |
dc.contributor.nonIdAuthor | Lee, Yongsun | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Annealing | - |
dc.subject.keywordAuthor | FeFETs | - |
dc.subject.keywordAuthor | Switches | - |
dc.subject.keywordAuthor | Iron | - |
dc.subject.keywordAuthor | Capacitors | - |
dc.subject.keywordAuthor | Grain size | - |
dc.subject.keywordAuthor | Insulators | - |
dc.subject.keywordAuthor | Ferroelectric field-effect transistor | - |
dc.subject.keywordAuthor | ferroelectrics | - |
dc.subject.keywordAuthor | nonvolatile | - |
dc.subject.keywordAuthor | relative permittivity | - |
dc.subject.keywordPlus | GRAIN-SIZE | - |
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