DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ha, Sangwoo | ko |
dc.contributor.author | Kim, Sangjin | ko |
dc.contributor.author | Han, Donghyeon | ko |
dc.contributor.author | Um, Soyeon | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2022-05-16T09:00:48Z | - |
dc.date.available | 2022-05-16T09:00:48Z | - |
dc.date.created | 2022-05-16 | - |
dc.date.created | 2022-05-16 | - |
dc.date.issued | 2022-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.69, no.5, pp.2433 - 2437 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | http://hdl.handle.net/10203/296552 | - |
dc.description.abstract | Computing-in-memory (CIM) shows high energy-efficiency through the analog DNN computation inside the memory macros. However, as the DNN size increases, the energy-efficiency of CIM is reduced by external memory access (EMA). One of the promising solutions is eDRAM based CIM to increase memory capacity with a high density cell. Although the eDRAM-CIM has a higher density than the SRAM-CIM, it suffers from both poor robustness and a low signal-to-noise ratio (SNR). In this brief, the energy-efficient eDRAM-CIM macro is proposed while improving computational robustness and SNR with three key features: 1) High SNR voltage-based accumulation with segmented BL architecture (SBLA), resulting in 17.1 dB higher SNR, 2) canceling PVT/leakage-induced error with common-mode error canceling (CMEC) circuit, resulting in 51.4% PVT variation reduction and 51.4% refresh power reduction, 3) a ReLU-based zero-gating ADC (ZG-ADC), resulting in ADC power reduction up to 58.1%. According to these new features, the proposed eDRAM-CIM macro achieves 81.5-to-115.0 TOPS/W energy-efficiency with 209-to-295 mu W power consumption when 4b x 4b MAC operation is performed with 250 MHz core frequency. The proposed macro also achieves 91.52% accuracy at the CIFAR-10 object classification dataset (ResNet-20) without accuracy drop even with PVT variation. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 36.2 dB High SNR and PVT/Leakage-Robust eDRAM Computing-In-Memory Macro With Segmented BL and Reference Cell Array | - |
dc.type | Article | - |
dc.identifier.wosid | 000790814000013 | - |
dc.identifier.scopusid | 2-s2.0-85126526096 | - |
dc.type.rims | ART | - |
dc.citation.volume | 69 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 2433 | - |
dc.citation.endingpage | 2437 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.identifier.doi | 10.1109/TCSII.2022.3159808 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Ha, Sangwoo | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Cell leakage-robust | - |
dc.subject.keywordAuthor | computing-in-memory (CIM) | - |
dc.subject.keywordAuthor | embedded DRAM | - |
dc.subject.keywordAuthor | error canceling | - |
dc.subject.keywordAuthor | high SNR | - |
dc.subject.keywordAuthor | PVT-robust | - |
dc.subject.keywordAuthor | zero-gating | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.