Porous layer based memristor device development and memristor evaluation system implementation

Abstract

Recently, owing to the development of artificial intelligence and machine learning, artificial neural network attracts a lot of attention. As data become more complex and large, power consumption and speed issue due to the bottleneck between memory and processor become serious issue in conventional von Neumann structure. For implementing non-von Neumann structure, where memory and processor is merged in one device, memristor, which changes its resistance depending on voltage apply, is a reliable candidate. However, conventional memristor device suffers from various flaws to be used as a neuromorphic device. Among them, uniformity issue is most crucial issue, which has a large impact on the accuracy of entire machine learning process. For these reason, there have been several attempts to mitigate this issue. However, they have several drawbacks such as low CMOS compatibility and impossibility of stack. In this study, porous layer based memristor is suggested as a device that has high temporal and spatial uniformity, 3D stack possibility and CMOS compatibility. By alleviating conventional issue of memristor, it paves the way for memristor to be utilized as a reliable neuromorphic device. Moreover, in order to operate and evaluate the memristor array by computer command, evaluation system is implemented with DAQ, FPGA and PCB.