DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Park, In-Cheol | - |
dc.contributor.advisor | 박인철 | - |
dc.contributor.author | Lee, Kyungpil | - |
dc.date.accessioned | 2022-04-27T19:31:15Z | - |
dc.date.available | 2022-04-27T19:31:15Z | - |
dc.date.issued | 2021 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=948729&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/295989 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2021.2,[iii, 28 p. :] | - |
dc.description.abstract | Fast Fourier transform (FFT) is widely used in the orthogonal frequency division multiplexing (OFDM) systems to overcome the issues related to the generation of orthogonal subcarriers. This paper proposes a plane-wise time-multiplexing processing as a simple FFT processing method for 5th generation (5G) new radio (NR) communication systems, and a hardware architecture for it. The proposed method simplifies the FFT processing required in the 5G NR communication systems by dividing the entire FFT into several planes and time-multiplexing them, which makes the very-large-scale integration (VLSI) design simple. In addition, in order to reduce the size of the memory that occupies most of the area of the FFT hardware, precision tapering is proposed based on the fundamental property of FFT hardware implementation. Simulation results show that the precision tapering reduces the sizes of the delay buffer and twiddle factor memory by 4.18% and 17.14%, respectively, for the proposed FFT hardware architecture, while maintaining the signal-to-quantization-noise-ratio (SQNR) obtained with the previous uniform precision structure. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | 5G new radio (NR)▼aorthogonal frequency division multiplexing (OFDM)▼afast Fourier transform (FFT)▼apipeline architecture▼afixed-point implementation▼aplane-wise time-multiplexing processing▼aprecision tapering | - |
dc.subject | 5세대 새로운 라디오▼a직교 주파수 분할 다중화▼a고속 푸리에 변환▼a파이프라인 아키텍처▼a고정 소수점 구현▼a평면 방식 시간 다중화 처리▼a정밀도 테이퍼링 | - |
dc.title | Area-efficient plane-wise FFT architecture for 5G NR communication systems | - |
dc.title.alternative | 5세대 통신 시스템을 위한 면적 효율적인 평면 방식 고속 푸리에 변환 아키텍처 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
dc.contributor.alternativeauthor | 이경필 | - |
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