Reinforcement learning based design of GDDR6 WCK for 20Gbps bandwidth

Abstract

To support high bandwidth for a graphic computing system, the data rate of GDDR6 is required to be over 20Gbps. It becomes extremely difficult to keep the date rate of GDDR6 at 2XGbps considering signal integrity (SI). To guarantee the SI of DQ, the skew of WCK, which is a data clock, must be minimized. From the verification process, we found that the speed of WCK skew and the data rate of GDDR6 are closely related. In this work, a WCK design optimization method using reinforcement learning is proposed to achieve over 20Gbps. As a result of training, the skew of WCK is successfully reduced to 70%. The proposed method is relatively simple and powerful because the circuit can be designed only with the target specification.