DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Cho, SeongHwan | - |
dc.contributor.advisor | 조성환 | - |
dc.contributor.author | Kim, Yongjo | - |
dc.date.accessioned | 2022-04-21T19:34:15Z | - |
dc.date.available | 2022-04-21T19:34:15Z | - |
dc.date.issued | 2021 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=962448&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/295700 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2021.8,[viii, 74 p. :] | - |
dc.description.abstract | This thesis introduces a quadrature signals corrector and generator for a low-power DDR4 mobile DRAM interface. A quadrature signal corrector for eliminating the phase imbalance among quadrature signals presents a shared digital feedback loop with a time-multiplexed loop filter. The proposed shared digital feedback loop can minimize the effect of circuit mismatch that hampers the phase accuracy. Furthermore, a self-calibrated offset delay that self-calibrates to delay corresponding to the quadrature-phase interval is proposed. It allows the use of a low-power 1-bit TDC instead of a power-hungry multi-bit TDC, and it also eliminates the effect of the remaining static mismatch in the shared feedback loop. A signal generator for controlling the noise of a signal source used to make a quadrature signal actively seeks so that the signal has the desired jitter performance with optimal power consumption. The signal's jitter performance and power consumption are adjusted using a power and noise trade-off of a ring voltage-controlled oscillator (VCO). Moreover, a PVT-tolerant on-chip jitter monitor circuit (JMC) that figures out the jitter performance of the signal is proposed. As a result, the proposed corrector and generator can provide an accurate quadrature signal with no phase imbalance and suitable jitter performance and power consumption for the application even under PVT-variation. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Low power DDR4▼aMobile DRAM interface▼aBang-bang phase detector (BBPD)▼aQuadrature clock signal corrector▼aSelf-calibrated offset delay▼aClock generator▼aPhase-locked loop(PLL)▼aJitter control loop(JCL)▼aOn-chip jitter monitor circuit(JMC)▼aNoise and power reconfigurable ring voltage controlled oscillator(VCO) | - |
dc.subject | 저전력 디디알4▼a모바일 디램 인터페이스▼a뱅-뱅 위상 검출기▼a쿼드러처 클락 신호 교정기▼a자가-교정 오프셋 딜레이▼a신호 생성기▼a위상 동기 루프▼a지터 컨트롤 루프▼a온-칩 지터 모니터 회로▼a잡음-전력 재구성 가능한 링 전압 제어 발진기 | - |
dc.title | Design of PVT-insensitive clock generator and clock corrector for precise quadrature generation | - |
dc.title.alternative | 정확한 쿼드러처 신호 생성을 위한 PVT 변화에 둔감한 클럭 생성기와 교정기의 설계 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
dc.contributor.alternativeauthor | 김용조 | - |
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