Low power ECG arrhythmia detection SoC with STT-MRAM and LDMAC unit

Abstract

Recently, low power deep neural network (DNN) inference system is emerged with wearable edge devices. However, previous DNN systems use volatile memory, which causes external memory access (EMA) and much power consumption during DNN inference. Therefore, non-volatile memory (NVM) is emerged as solution for low power consumption with zero external memory access (ZMA). In the paper, a low power spin-transfer-torque magnetic RAM (STT-MRAM) based mixed-mode electrocardiogram (ECG) arrhythmia monitoring SoC is proposed. The proposed SoC consists of 1 MB STT-MRAM, leakage-based delay multiply-and-accumulation (MAC) unit (LDMAC), and ECG analog-front-end (AFE). ResNet structure with 16 1-D convolution layers and max-pooling layers is adopted for the ECG arrhythmia detection with weight reusing and partial sum reusing scheme. A non-volatile 1 MB STT-MRAM enables DNN inference to achieve higher area efficiency, lower power consumption without external memory access. The proposed mixed-mode LDMAC consumes only 4.11 nW MAC power by reusing leakage current. The proposed SoC is fabricated in 28nm FDSOI process with 7.29mm^2 area. It demonstrates ECG arrhythmia detection with 85.1% accuracy, which is the highest score reported, and the lowest power consumption of 1.02 μW. Keyword spotting (KWS) IC is also proposed in the paper for low power user interface in wearable devices. The proposed KWS IC is composed of feature extraction block with FFT block and rectangular filter array, and MRAM-processing-in-memory (PIM) block for low power MAC operations. Binary KWS algorithm with 4 convolution layers and 2 fully-connected layers is used for high keyword recognition accuracy. The proposed KWS IC shows 4.5 μW power consumption with 90.7% keyword recognition accuracy.