A Polar-Demodulation-Based Impedance-Measurement IC Using Frequency-Shift Technique With Low Power Consumption and Wide Frequency Range

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In this paper, we present a new impedance measurement integrated circuit (IC) for achieving a wideband coverage up to 10 MHz and low power consumption. A frequency-shift technique is applied to down-shift the input frequency, which ranges from 100 kHz to 10 MHz, into an intermediate frequency of 10 kHz, while the frequency-shifting is bypassed when the input frequency falls in the range from 100 Hz to 100 kHz. It results in 100 times relaxation of the requirement on the instrumentation amplifier (IA) bandwidth and the comparator delay, greatly reducing overall power consumption. The proposed IC employs the polar demodulation structure with a reference resistor that provides reference timing information avoiding any synchronization issue with the transmitter. In order to compensate for the comparator delay and nonlinearity of the IA, the reference magnitude measurement path is added, making only the mismatch of the circuit affects the accuracy. This allows for employing the auto-zeroing technique that can remove the offset but increase the absolute delay by using an additional capacitor to the comparator. The chip fabricated in a 0.18-mu m CMOS technology consumes the power of 756 mu W while covering the measurement frequency range from 100 Hz to 10 MHz and exhibiting the maximum magnitude and phase errors of 1.1% and 1.9 degrees, respectively.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2021-12
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, v.15, no.6, pp.1210 - 1220

ISSN
1932-4545
DOI
10.1109/TBCAS.2021.3135836
URI
http://hdl.handle.net/10203/295144
Appears in Collection
EE-Journal Papers(저널논문)
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