DC Field | Value | Language |
---|---|---|
dc.contributor.author | 방주은 | ko |
dc.contributor.author | 조용우 | ko |
dc.contributor.author | 최서진 | ko |
dc.contributor.author | 최재혁 | ko |
dc.date.accessioned | 2021-12-14T06:44:59Z | - |
dc.date.available | 2021-12-14T06:44:59Z | - |
dc.date.created | 2021-12-13 | - |
dc.date.issued | 2021-01 | - |
dc.identifier.citation | IDEC Journal of Integrated Circuits and Systems, v.7, no.1, pp.18 - 23 | - |
dc.identifier.issn | 2384-2113 | - |
dc.identifier.uri | http://hdl.handle.net/10203/290567 | - |
dc.description.abstract | A DCO was designed for an ultra-low-jitter digital sub-sampling PLL. To suppress the enormous amount of quantization noise, a very fine frequency resolution is critical. Also, the phase noise of an LC VCO itself is crucial for ultra-low-jitter applications. For high-performance LC VCO design, a basic insight into the oscillator is needed. The proposed DCO consists of a string-type RDAC, MASH 1-1 DSM, and CMOS-type cross-coupled LC VCO. The frequency resolution is significantly increased by using the DSM. The proportional path has a 17-bit resolution, while the integral path has an 18-bit resolution. The DSM operates at 400 MHz, and its quantization noise is canceled by the 2nd-order low-pass filter at the output of the DAC. By adopting 2nd-order noise shaping, the quantization noise at the PLL output is negligible. The DAC was designed with a string resistor topology for its design simplicity and relieved target specifications. The DCO has a 12 to 14.5 GHz frequency tuning range. The phase noise at a 1 MHz offset frequency is –109 dBc/Hz at a 14-GHz output. The average power consumption is 5.5 mW. The calculated FOM at a 1-MHz offset frequency is –184.5 dB. | - |
dc.language | English | - |
dc.publisher | 한국과학기술원 반도체설계교육센터 | - |
dc.title | Design of a 12 to 14.5 GHz Digitally-Controlled Oscillator for an Ultra-Low-Jitter PLL | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.citation.volume | 7 | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 18 | - |
dc.citation.endingpage | 23 | - |
dc.citation.publicationname | IDEC Journal of Integrated Circuits and Systems | - |
dc.identifier.kciid | ART002665198 | - |
dc.contributor.localauthor | 최재혁 | - |
dc.contributor.nonIdAuthor | 최서진 | - |
dc.description.isOpenAccess | N | - |
dc.subject.keywordAuthor | Delta-Sigma Modulator (DSM) | - |
dc.subject.keywordAuthor | Digital-to-Analog Converters (DAC) | - |
dc.subject.keywordAuthor | Digitally-Controlled Oscillator (DCO) | - |
dc.subject.keywordAuthor | LC-VCO | - |
dc.subject.keywordAuthor | Phase-Locked Loop | - |
dc.subject.keywordAuthor | Phase noise | - |
dc.subject.keywordAuthor | Sub-sampling | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.