대형 Adder Tree 구조에최적화된덧셈기를위한효율적인 XOR 논리회로연구 GEP-111

Abstract

Today, machine learning forms main stream in many research areas with respect to software and hardware. In the hardware design area, efficient convolution processing is one of the main research topics. Convolution comprises of many multiplications followed by additions of the results. Because this operation is costly, efficient multiplication unit is important to design low power hardware. To make low power multiplication unit, the adder tree to sum the partial outputs is the key point for optimization. Normally, an adder tree based on compressors and carry-save adders is used to make efficient adder tree. Because such adder structures do not have long carry propagation path, carry is not critical than sum unlike the normal adder. Therefore, making the sum in the full adder should be improved. To improve processing of the sum, this paper tries to find an optimal 3-input XOR gate circuit. There are many designs for 3-input XOR gates. The XOR gate proposed in this paper occupies small area (x 0.71), consumes low power (x 0.5) than a traditional 3-input XOR gate.