DC Field | Value | Language |
---|---|---|
dc.contributor.author | Koh, Seok Tae | ko |
dc.contributor.author | Lee, Jihun | ko |
dc.contributor.author | Gang, Gyeong-Gu | ko |
dc.contributor.author | HAN, HYUNKI | ko |
dc.contributor.author | Kim, Hyun-Sik | ko |
dc.date.accessioned | 2021-11-26T06:40:31Z | - |
dc.date.available | 2021-11-26T06:40:31Z | - |
dc.date.created | 2021-11-25 | - |
dc.date.created | 2021-11-25 | - |
dc.date.created | 2021-11-25 | - |
dc.date.created | 2021-11-25 | - |
dc.date.issued | 2021-12 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.12, pp.3593 - 3607 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/289507 | - |
dc.description.abstract | For fast buffering of large stepwise input to an nF-range capacitive load, this article presents a 5-V rail-to-rail (RTR) input–output paralleled-amplifier (PA) in which a dynamic class-C amplifier (DCCA) and a linear single-stage operational transconductance amplifier (OTA) are combined in parallel. During slew time, the DCCA, which is designed to consume a near-zero static current, dominantly supplies the dynamic current up to 8.5 mA to the output. When the output gets closer to the fine-settling region, the DCCA is rapidly faded out in virtue of a dedicated near-zero dead-zone control (NDZC), and it hands over to the linear OTA. A current-redistributive RTR Gm -boosting technique is also proposed so that the OTA can have a wide gain-bandwidth product (GBW) even over the RTR input range while minimizing the quiescent current dissipation. The prototype chip was fabricated only with 0.5- μm 5-V CMOS devices, and it occupies a die area of 0.03 μm2 . The proposed amplifier consumed a static current of 3.1 μA with a supply voltage of 5 V. The slew rates (SRs) with load capacitances ( CL ) of 0.8 and 10 nF were measured to be 10.3 and 0.86 V/ μs , respectively, for a step input of Δ 4.2 V, which is a state-of-the-art result compared to prior chips. The measured GBW of 10–127 kHz was achieved over 0.8–10 nF CL with ≥ 59° phase margin (PM). The measured GBW deviation in a common-mode voltage ( VCM ) range of 0.3–4.7 V was within the maximum of 20%. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 5-V Dynamic Class-C Paralleled Single-Stage Amplifier With Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique | - |
dc.type | Article | - |
dc.identifier.wosid | 000722004000010 | - |
dc.identifier.scopusid | 2-s2.0-85112144080 | - |
dc.type.rims | ART | - |
dc.citation.volume | 56 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 3593 | - |
dc.citation.endingpage | 3607 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/jssc.2021.3101895 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Kim, Hyun-Sik | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Dynamic class-C amplifier (DCCA) | - |
dc.subject.keywordAuthor | operational transconductance amplifier (OTA) | - |
dc.subject.keywordAuthor | output buffer | - |
dc.subject.keywordAuthor | paralleled amplifier (PA) | - |
dc.subject.keywordAuthor | rail-to-rail (RTR) | - |
dc.subject.keywordAuthor | slew rate (SR) | - |
dc.subject.keywordAuthor | transconductance (G(m))-boosting | - |
dc.subject.keywordPlus | RECYCLING FOLDED CASCODE | - |
dc.subject.keywordPlus | 3-STAGE AMPLIFIER | - |
dc.subject.keywordPlus | CAPACITIVE LOAD | - |
dc.subject.keywordPlus | COLUMN DRIVER | - |
dc.subject.keywordPlus | SLEW-RATE | - |
dc.subject.keywordPlus | BUFFER | - |
dc.subject.keywordPlus | COMPENSATION | - |
dc.subject.keywordPlus | FEEDFORWARD | - |
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