A 5-V Dynamic Class-C Paralleled Single-Stage Amplifier With Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique

Abstract

For fast buffering of large stepwise input to an nF-range capacitive load, this article presents a 5-V rail-to-rail (RTR) input–output paralleled-amplifier (PA) in which a dynamic class-C amplifier (DCCA) and a linear single-stage operational transconductance amplifier (OTA) are combined in parallel. During slew time, the DCCA, which is designed to consume a near-zero static current, dominantly supplies the dynamic current up to 8.5 mA to the output. When the output gets closer to the fine-settling region, the DCCA is rapidly faded out in virtue of a dedicated near-zero dead-zone control (NDZC), and it hands over to the linear OTA. A current-redistributive RTR Gm -boosting technique is also proposed so that the OTA can have a wide gain-bandwidth product (GBW) even over the RTR input range while minimizing the quiescent current dissipation. The prototype chip was fabricated only with 0.5- μm 5-V CMOS devices, and it occupies a die area of 0.03 μm2 . The proposed amplifier consumed a static current of 3.1 μA with a supply voltage of 5 V. The slew rates (SRs) with load capacitances ( CL ) of 0.8 and 10 nF were measured to be 10.3 and 0.86 V/ μs , respectively, for a step input of Δ 4.2 V, which is a state-of-the-art result compared to prior chips. The measured GBW of 10–127 kHz was achieved over 0.8–10 nF CL with ≥ 59° phase margin (PM). The measured GBW deviation in a common-mode voltage ( VCM ) range of 0.3–4.7 V was within the maximum of 20%.