Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD

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dc.contributor.authorKim, Jihoko
dc.contributor.authorJung, Myoungsooko
dc.contributor.authorKim, Johnko
dc.date.accessioned2021-11-09T06:43:21Z-
dc.date.available2021-11-09T06:43:21Z-
dc.date.created2021-11-09-
dc.date.created2021-11-09-
dc.date.created2021-11-09-
dc.date.created2021-11-09-
dc.date.created2021-11-09-
dc.date.issued2021-07-
dc.identifier.citationIEEE COMPUTER ARCHITECTURE LETTERS, v.20, no.2, pp.150 - 153-
dc.identifier.issn1556-6056-
dc.identifier.urihttp://hdl.handle.net/10203/288978-
dc.description.abstractModern NAND Flash memory-based Solid State Drive (SSD) is designed to support high bandwidth for I/O requests by exploiting various parallelism including multiple channels, multiple flash memory chips, and multiple planes. However, SSD system is utilized not only for general I/O requests but is also used during flash memory management processes (e.g., garbage collection). In particular, the sharing of system resources (e.g., system bus, DRAM) for I/O requests and garbage collection can cause performance degradation. In this letter, we address the system bus bottleneck and propose Decoupled SSD system that decouples the front-end (i.e. cores, system bus) with the back-end (i.e., flash memory) and provide an on-chip network to interconnect the controllers together. Our decoupled SSD enables advanced command (i.e. copy-back) to be exploited for efficient garbage collection; in particular, we propose to extend copy-back commands to enable global copy-back through the flash-controller interconnect to effectively decouple I/O path and garbage collection path. Our evaluations show that decoupled SSD results in up to 34.7% bandwidth improvement, for I/O traffic while achieving up to 69% speedup for garbage collection.-
dc.languageEnglish-
dc.publisherIEEE COMPUTER SOC-
dc.titleDecoupled SSD: Reducing Data Movement on NAND-Based Flash SSD-
dc.typeArticle-
dc.identifier.wosid000712561700001-
dc.identifier.scopusid2-s2.0-85117086057-
dc.type.rimsART-
dc.citation.volume20-
dc.citation.issue2-
dc.citation.beginningpage150-
dc.citation.endingpage153-
dc.citation.publicationnameIEEE COMPUTER ARCHITECTURE LETTERS-
dc.identifier.doi10.1109/LCA.2021.3118688-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorJung, Myoungsoo-
dc.contributor.localauthorKim, John-
dc.contributor.nonIdAuthorKim, Jiho-
dc.description.isOpenAccessN-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorAsh-
dc.subject.keywordAuthorBandwidth-
dc.subject.keywordAuthorError correction codes-
dc.subject.keywordAuthorTopology-
dc.subject.keywordAuthorRandom access memory-
dc.subject.keywordAuthorSystem-on-chip-
dc.subject.keywordAuthorFlash memories-
dc.subject.keywordAuthorSolid-state drive-
dc.subject.keywordAuthorflash memory-
dc.subject.keywordAuthorcopy-back-
dc.subject.keywordAuthorinterconnection networks-
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