A 170MHz-Lock-In-Range and-253dB-FoM(jitter), 12-to-14.5GHz Subsampling PLL with a 150 mu W Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator

Abstract

Sub-sampling PLLs (SSPLLs) are popular for generating low-jitter output signals. However, the critical problem of SSPLLs is that they do not use a frequency divider, so the lock-in range is strictly limited. The lock-in range is defined as the maximum instantaneous disturbance at which the PLL can recover its output frequency, fOUT, to the target frequency, fTA, [1], and the lock-in range of SSPLLs generally is restricted to less than 40% of the reference frequency, fREF [2]. As shown at the top left of Fig. 17.8.1, if a sudden frequency disturbance, fD, occurring through the supply or the control voltage is within the lock-in range, it can be corrected by the PLL, allowing fOUT to be recovered as fTA. However, if fD exceeds the lock-in range, it causes lock failure or false locking. As fOUT increases, the external disturbance with the same magnitude causes a larger fD which implies that the problem of the lock-in range is more serious when we aim for a higher fOUT given fTA. Despite their popularity, conventional frequency-locked loops (FLLs) [3], [4] require large power due to dividers operating at fOUT, To save power, the FLL in [2] operates once every 200 reference cycles, but this method has a problem in that the fD-detecting time increases in inverse proportion to the duty cycle of the FLL, which increases the overall frequency re-acquisition time, fRA. Another solution is to extend the lock-in range by increasing fREF However, when a reference multiplier is used in a conventional way, it requires large power, since every edge at the output must have very low jitter [5] to avoid deteriorating the PLL output jitter. It also degrades the resolution of the fOUT of integer-N PLLs [6].