DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Kyung-Sik | ko |
dc.contributor.author | Kim, Keun-Mok | ko |
dc.contributor.author | Ko, Jinho | ko |
dc.contributor.author | Lee, Sang-Gug | ko |
dc.date.accessioned | 2021-10-21T01:30:15Z | - |
dc.date.available | 2021-10-21T01:30:15Z | - |
dc.date.created | 2021-10-19 | - |
dc.date.issued | 2020-11 | - |
dc.identifier.citation | IEEE Asian Solid-State Circuits Conference (A-SSCC) | - |
dc.identifier.uri | http://hdl.handle.net/10203/288290 | - |
dc.description.abstract | This paper presents a 915 MHz binary frequencyshift keying (BFSK) internet of things (IoT) transmitter (TX) utilizing a frequency tripler driven by duty and phase calibrated signal. The proposed frequency tripling method is adopted to suppress the unwanted harmonic spurs generated from the conventional frequency tripler followed by a class-D power amplifier (PA), relaxing the requirement for the harmonic filtering at the PA output. Implemented in a 55 nm CMOS, the proposed TX achieves the output power of 5 dBm and efficiency of 30.6% with an on-chip PA matching network (MN) while dissipating a dc power of 210 mu W in the synthesizer. | - |
dc.language | English | - |
dc.publisher | IEEE | - |
dc.title | A 5 dBm 30.6% Efficiency 915 MHz Transmitter with 210 mu W ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer | - |
dc.type | Conference | - |
dc.identifier.wosid | 000654231500032 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | IEEE Asian Solid-State Circuits Conference (A-SSCC) | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | Virtual | - |
dc.contributor.localauthor | Lee, Sang-Gug | - |
dc.contributor.nonIdAuthor | Ko, Jinho | - |
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