DC Field | Value | Language |
---|---|---|
dc.contributor.author | Chang, Dong-Jin | ko |
dc.contributor.author | Choi, Michael | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2021-09-26T01:30:41Z | - |
dc.date.available | 2021-09-26T01:30:41Z | - |
dc.date.created | 2021-09-24 | - |
dc.date.created | 2021-09-24 | - |
dc.date.created | 2021-09-24 | - |
dc.date.created | 2021-09-24 | - |
dc.date.issued | 2021-09 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.56, no.9, pp.2691 - 2700 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/287861 | - |
dc.description.abstract | This article presents a relative-prime-based time-interleaved (RP TI) sub-ranging successive-approximation register (SAR) analog-to-digital converter (ADC) with on-chip background skew calibration. The proposed calibration aligns the sampling time of every fine ADC (F-ADC) to that of a particular coarse ADC (C-ADC) that works as a reference ADC. To avoid the unwanted calibration tone from the reference ADC, the C-ADC is also time-interleaved to make all samples undergo the same kick back. By setting the numbers of the time-interleaved channels of the C-ADCs and F-ADCs in a relative-prime relationship, every C-ADC can be evenly shared by every F-ADC; thus, the timing skews between the interleaved sub-ADCs are calibrated by adjusting the sampling edges of every F-ADC to the particular C-ADC working as a reference ADC. An 18-channel TI 10-bit 2.2-GS/s SAR ADC was implemented as a prototype with 28-nm CMOS. Owing to the proposed on-chip background skew calibration, the peak tone by skew was reduced by 23 dB from -40 to -63 dB, which corresponds to the residual skew reduction from 1.6 ps to 113 fs near the Nyquist input. Thus, the prototype ADC achieved a spurious free dynamic range (SFDR) over 52.8 dB and a signal-to-noise-and-distortion ratio (SNDR) over 44.9 dB with 18.2-mW power consumption, which leads to a Walden figure-of-merit (FoM) of 57.8 fJ/conversion-step. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration | - |
dc.type | Article | - |
dc.identifier.wosid | 000690441300009 | - |
dc.identifier.scopusid | 2-s2.0-85105115219 | - |
dc.type.rims | ART | - |
dc.citation.volume | 56 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 2691 | - |
dc.citation.endingpage | 2700 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2021.3073976 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Choi, Michael | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Calibration | - |
dc.subject.keywordAuthor | Timing | - |
dc.subject.keywordAuthor | Computer architecture | - |
dc.subject.keywordAuthor | Time-frequency analysis | - |
dc.subject.keywordAuthor | Redundancy | - |
dc.subject.keywordAuthor | Prototypes | - |
dc.subject.keywordAuthor | Linearity | - |
dc.subject.keywordAuthor | Analog-to-digital converter (ADC) | - |
dc.subject.keywordAuthor | digital background calibration | - |
dc.subject.keywordAuthor | sub-ranging architecture | - |
dc.subject.keywordAuthor | time-interleaved (TI) ADC | - |
dc.subject.keywordAuthor | timing-skew mismatch | - |
dc.subject.keywordPlus | DB SNDR | - |
dc.subject.keywordPlus | NM CMOS | - |
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