Calibration techniques for high resolution and high speed time-interleaved SAR ADCs

Abstract

This paper proposes various digital calibration techniques for time-interleaved (TI) analog-to-digital converters (ADCs). Though TI ADC has an advantage in speed, there are many channel-mismatch issues such as gain, offset, and timing skew. In addition, owing to the power efficient and digital-friend characteristic of successive approximation register (SAR) ADC, SAR ADCs become popular structure and are utilized each channel of TI ADC. Hence, proposed digital calibration for TI ADCs is based on SAR ADC structure for following nowadays trend of ADC. First, this paper proposes a linearity calibration algorithm of a capacitive digital-to-analog converter (CDAC) for SAR ADCs based on a normalized-full-scale of the DAC. Since the capacitor weight errors are represented as the difference between the real and ideal weights with respect to the normalized-full-scale, the calibrated digital representation of CDAC does not have gain error among ADCs in TI structure. A model of a 14-bit-format SAR ADC with a segmented CDAC by a bridge capacitor is simulated to demonstrate the performance of the proposed calibration algorithm. The effective number of bits (ENOB) and spurious-free dynamic range (SFDR) of the 14-bit-format ADC model are improved to 13.2 bits and 94.0 dB from 8.4 bits and 54.8 dB, respectively, at a standard deviation of a unit capacitor of 2%. The gain-error-free characteristic of the proposed linearity calibration algorithm is verified with a 2-channel TI SAR ADC model. Second, this paper proposes a digital calibration algorithm of timing skew. Many previously reported solutions have relied on statistical property of input signal and, thus, required considerable number of samples, which makes on-chip skew calibration difficult. In this work, the 1b deterministic calculation of the proposed skew calibration function could be implemented compact on-chip. The timing skews between the interleaved sub ADCs are calibrated by adjusting the time-skew of all fine ADCs to that of a certain coarse ADC as a reference, by virtue of the single channel ADC structure of SAR-SAR sub-ranging, where every coarse SAR ADC is evenly shared by every fine SAR ADC. The prototype ADC is fabricated in 40nm CMOS process. Although first chip is not success for meeting target performance, the source of error is analyzed and properly revised. The post-layout simulation verifies the revised chip and board issue such as bonding is also considered. The estimated performance shows to state-of-the-art by compared to the other previous works.