Time-domain interpolation technique for low-power time-interleaved ADC

Abstract

High-speed wireless communication systems such as impulse radio ultra-wideband (UWB) and 60-GHz short-range radio receivers require low-resolution (3-6 bits) and over-GHz sampling ADCs. The characteristics of input bandwidth, sampling rate, effective resolution, and power consumption of the ADC have a significant impact on the performance of the systems. In this thesis, a compact 8x interpolating flash ADC architecture is proposed to reduce the hardware burden, input capacitance and power consumption. In addition, the proposed 8x interpolating flash ADc is applied to time-interleaved (TI) ADC and two-step flash ADC to improve the power consumption and operating speed of the ADC. In Chapter 1, A 6-bit 2.5-GS/s 8x dynamic interpolating flash analog-to-digital converter (ADC) with an offset calibration technique for interpolated voltage-to-time converters (VTCs) is presented for high speed applications. Also, A 6-bit 4x TI time-domain interpolating flash ADC is presented using the proposed 8x interpolating flash ADCs. The dynamic-amplifier-structured VTC enables linear zero-crossing (ZX) interpolation in the time-domain with an interpolation factor of eight, which reduces the number of front-end VTCs to one-sixth the original structure. The reduced number of VTCs lowers the power consumption, load capacitance to the track-and-holder (T/H), and overhead of VTC offset calibration. The prototype 6-bit 2.5-GS/s flash ADC was implemented in a 65 nm CMOS process and occupies a $0.12 mm^2$ chip area, including offset calibration circuitry. With a 1.23GHz input, the measured SNDR and SFDR are 33.84 dB and 45.07 dB, respectively, with power consumption of 7.5 mW under a supply voltage of 0.85 V. The prototype 6-bit 10-GS/s 4x TI flash ADC was implemented in a 65-nm CMOS process and occupied $0.5 mm^2$ including a 4-to-1 output MUX and 243-times output decimator. The ADC achieves SNDR of 28.9 dB at Nyquist input and a total power consumption of 63 mW under supplies of 0.85 V and 1.1 V for the ADC cores and clock generator + T/Hs, respectively. In Chapter 2, A 7-bit 3-GS/s two channels TI two-step flash ADC with 7-GHz effective resolution bandwidth (ERBW) is presented for high speed applications. The reference embedded flash ADC in the fine stage requires only one capacitive digital-to-analog converter (C-DAC), which can improve power consumption, area and input bandwidth. Since the input nodes of the coarse and fine ADCs are separated into the bottom and top plate nodes of the C-DAC, respectively, time consuming pre-charge operation and gain error between the coarse and fine ADCs can be eliminated. The fine ADC employs 8x interpolation technique to facilitate the reference embedding and compact design. The prototype ADC was implemented in a 40 nm CMOS process and occupies a $0.03 mm^2$ including the offset calibration circuitry. With a 1.49-GHz input, the measured SNDR and SFDR are 39.94 dB and 55.80 dB, respectively. The ERBW with and without time skew calibration are about 4.8-GHz and 7-GHz, respectively, thanks to the reference embedded fine ADC. The power consumption is 7.6-mW under a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 31.3 fJ/conversion-step at 3-GS/s.