Memory architecture for improving reliability of phase change memory

Abstract

Phase Change Memory (PCM) becomes a candidate of a new main memory or a storage class memory, as scaling down DRAM becomes ever more difficult. However, PCM reliability issues such as Write Disturbance (WD) and Write Endurance (WE) should be solved to use it in real computing systems. WD errors are caused by resistance reductions in a cell by frequently writing adjacent cells. Meanwhile, writing to the same cell frequently makes the cell cannot store data anymore due to cell malfunction. This cell lifetime can be considered as WE. This dissertation shows approaches to mitigate WD and WE problems while taking system performance account. First, DC-PCM is a memory architecture to minimize WD errors. Additional cells called Detection Cells (DC) are allocated to a memory-line. DC-PCM can pre-detect WD errors in a memory-line, by applying schemes to generate WD errors in DCs earlier than those of normal cells in the corresponding memory-line. In addition, additional processing times are hidden, by processing operations to give DCs higher WD-vulnerability or to check WD errors in DCs during a WRITE. Second, Zero Comparison Write (ZCW) focused on improving WE with low WRITE processing time. Zero Comparison Write (ZCW) performs input and stored bit comparison only for each cell where '0' input bit will be written, and, for each '1' input bit, performs '1' WRITE which has different processing time depending on '0' ratio of the WRITE data and hard error information.