DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Bae, Hyeon-Min | - |
dc.contributor.advisor | 배현민 | - |
dc.contributor.author | Jeon, Sejun | - |
dc.date.accessioned | 2021-05-11T19:41:09Z | - |
dc.date.available | 2021-05-11T19:41:09Z | - |
dc.date.issued | 2018 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=886617&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/283434 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2018.2,[iv, 51 p. :] | - |
dc.description.abstract | A 20 Gb/s serial link transceiver employing a framed-pulsewidth modulation (FPWM) scheme that overcomes the SNR degradation without linearity requirement is presented. The FPWM scheme encodes data at the location and the width of pulses in a frame spanning multiple UIs while maintaining a minimum pulsewidth equal to 1UI. The test-chip achieves a coding gain of 33%, which allows the total throughput of 20 Gb/s while keeping the baud rate of 15 Gb/s. The equalization core incorporating programmable 3-tap pre-emphasis at transmitter and continuous-time linear equalizer (CTLE) at receiver compensates for channel insertion loss up to 12 dB at the baud frequency. The transceiver IC, fabricated in 40 nm CMOS, occupies $2.2 \times 0.48 mm^2$ and consumes 90.6 mW from a 0.9 V supply. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Pulsewidth modulation▼aSpectral efficiency▼aClock and data recovery (CDR)▼aSerial link▼aTransceiver | - |
dc.subject | 펄스 폭 변조▼a스펙트럼 효율▼a클락 및 데이터 혹원 회로▼a직렬 링크▼a송수신기 | - |
dc.title | (A) framed-pulsewidth-modulation scheme for next generation high-speed communication links | - |
dc.title.alternative | 차세대 고속 통신 링크를 위한 프레임 기반의 펄스 폭 변조 기술 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
dc.contributor.alternativeauthor | 전세준 | - |
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