Improving the performance and energy efficiency of the virtual memory system by skipping unnecessary translations and dynamically adjusting HW translation coverage

Abstract

Virtual memory provides rich functionality for the program developer. However, address translation accompanies the virtual memory system, requiring an address translation for every memory access. Recently with the rise of big memory systems and big memory workloads the virtual memory address translation system has been suffering great misses, resulting in significant performance overhead. This dissertation focuses on improving the virtual memory translation system with two approaches. Firstly, the virtual memory system design is revisited, and the cache hierarchy is modified to allow skipping of unnecessary address translations. Secondly, the page table is extended and hardware support is added to improve translation coverage of the translation lookaside buffer (TLB).

Based on the virtual caching concept, the first part of this dissertation proposes a hybrid virtual memory architecture extending virtual caching to the entire cache hierarchy, aiming to improve both performance and energy consumption by delaying translation. For large memory applications, delayed translation alone cannot solve the address translation problem, as fixed-granularity delayed TLBs may not scale with the increasing memory requirements. To mitigate the translation scalability problem, this study proposes a delayed many segment translation designed for the hybrid virtual caching. The experimental results show that our approach effectively lowers accesses to the TLBs, leading to significant power savings. In addition, the approach provides performance improvement with scalable delayed translation with variable length segments.

Under fragmented and diverse memory allocations that occur due to diverse execution environ- ments and memory heterogeneity, the second part of this dissertation proposes a novel HW-SW hybrid translation architecture, which can adapt to different memory mappings efficiently. The most important benefit of hybrid coalescing is its ability to change the coverage of the anchor entry dynamically, reflecting the current allocation contiguity status. By using the contiguity information directly set by the operating system, the technique can provide scalable translation coverage improvements with minor hardware changes, while allowing the flexibility of memory allocation. Our experimental results show that across diverse allocation scenarios with different distributions of contiguous memory chunks, the proposed scheme can effectively reap the potential translation coverage improvement from the existing contiguity.