DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Lee, Hee Chul | - |
dc.contributor.advisor | 이희철 | - |
dc.contributor.author | Kim, Chiyeon | - |
dc.date.accessioned | 2021-05-11T19:38:54Z | - |
dc.date.available | 2021-05-11T19:38:54Z | - |
dc.date.issued | 2019 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=871485&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/283310 | - |
dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2019.8,[v, 75 p. :] | - |
dc.description.abstract | In this dissertation, three types of readout circuits that useful in missile application systems are proposed. The first circuit is an asynchronous self-controlled two-gain-mode readout circuit, the second circuit is a high-dynamic-range readout circuit with multiple reset control technique, and the third circuit is a low power and high sensitivity readout circuit with clock gating double-edge-triggered flip-flop. The first circuit performs self-controlled two-gain-mode operation of the integration capacitor according to the input signal. These operations are performed asynchronously for each pixel during the integration of the photocurrent to respond promptly to rapidly changing situations. The measured results show that the proposed circuit operates normally according to the input-signal current and has better SNR than the conventional circuit in the case of a low-input-signal current. The second circuit was proposed to provide the higher dynamic range by performing multiple reset control of the integration capacitor according to the input signal. The pulse generation circuit and two-bit counter suitable for small pixel size enable multiple reset control operation. The proposed circuit has a dynamic range of 99.2 dB with good SNR for a wide range of input signals, good linearity of 99.9%, and a high frame rate of 200 Hz. The third circuit was designed for a low power, high sensitivity readout circuit that reduces errors within the final output signal and the power consumption. A capacitor-reset block employing a double-edge-triggered D flip-flop can facilitate reduction of errors within the final output signal. In addition, An asynchronous clock-gating technique in combination with readout circuit internal signal can reduce power consumption within $128 \times 128$ arrays. In the case of a low-input-signal current, the power consumed by the proposed circuit can be reduced to 2.3% and 1.4% of that consumed by the high-dynamic-range readout circuits with 10-MHz and 20-MHz clocks, respectively. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | Missile application system▼amid-wavelength infrared▼areadout integrated circuit▼aself-controlled two-gain-mode▼amultiple reset control▼adouble-edge-triggered flip-flop▼aclock gating | - |
dc.subject | 미사일 적용 시스템▼a중 적외선▼a신호취득회로▼a이득 자체 제어 모드▼a다중 리셋 제어▼a이중 에지 트리거 플립 플롭▼a클럭 게이팅 | - |
dc.title | (A) study on improvement of dynamic range and output characteristic of readout integrated circuit for mid-wavelength infrared detector | - |
dc.title.alternative | 중 적외선 검출기를 위한 신호취득회로의 동적 범위 향상 및 출력 특성 개선에 관한 연구 | - |
dc.type | Thesis(Ph.D) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
dc.contributor.alternativeauthor | 김치연 | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.