Characterizing inter-cell interference of 3D NAND flash memory and compensating the interference in real time

Abstract

The rapid development of information technology has resulted in explosive data growth, and the use of solid state drives (SSDs) with NAND flash is ever increasing to store data. In order to increase the cell density of the three-dimensional NAND flash memory (3D NAND), the number of stacked layers along with the inter-cell interference are increasing. However, compared to the 2D NAND flash memory, it was difficult to analyze 3D NAND due to the complex interference mechanisms. In this thesis, we have introduced a signal processing approach of evaluating the amount of interference based on the program state of the cell. For the 3D NAND with complex physical structure, statistical channel characteristics were evaluated to identify the main interference cells. The amount of interference caused by the main interference cells was about 20\% of the cell distribution margin. Hence, we conlude that a solution is needed for combating the increasing interference in the future. We modeled the 3D NAND channel by interference and noise between the victim cell and the main interference cell, and predicted the improvement of the data error rate when the interference was compensated. We confirmed that performance improvement can be guaranteed up to 50%. Finally, we proposed applying the interference compensator to the NAND application controller. Since the interference compensator must operate in real time during the read operation, in order to reduce the amount of signal processing, we have extracted the victim cells only for the cells in the overlapping region of the cell distribution, which is expected to have a high data error rate. We also showed how to correct the data only by the program state of the interference cells. The interference value to be compensated can be estimated by the program state of the victim and interfering cells and the estimation accuracy is controlled by adjusting the number of dominant interference cells according to the acceptable read latency. The simulation results show that the proposed interference compensation method can greatly reduce the error. To further increase real-time applicability, we proposed an algorithm that compensator operates by distinguishing only certain program states that need to be corrected. This enables to reduce the read latency which is increased due to the division of the program state of the interference cell. In order to increase the cell density, the error rate is increasing with the increase of the stacking of the three dimensional NAND. In addition, the decoding burden of storage systems is increasing as the number of bits stored in one cell increases. To solve these problems, we propose to configure the interference compensator additionally to the storage system.