Time-interleaved DAC with current integration-based clock phase calibration고속 동작을 위한 시간 교차 방식의 디지털 아날로그 변환기와 클럭 위상 보정법
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | Ryu, Seung-Tak | - |
| dc.contributor.advisor | 류승탁 | - |
| dc.contributor.author | Kim, Woo-Cheol | - |
| dc.date.accessioned | 2021-05-11T19:38:40Z | - |
| dc.date.available | 2021-05-11T19:38:40Z | - |
| dc.date.issued | 2019 | - |
| dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=871471&flag=dissertation | en_US |
| dc.identifier.uri | http://hdl.handle.net/10203/283296 | - |
| dc.description | 학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2019.8,[iv, 47 p. :] | - |
| dc.description.abstract | This paper presents a four-channel time-interleaved high-speed current-steering DAC with a proposed two-stage analog multiplexer (MUX). Optimum switching times of the cascaded MUX and the sub-DACs are guaranteed by background clock phase calibration with a proposed maximum-overlap-based phase detector. A 6b 28GS/s prototype DAC fabricated in 40nm CMOS achieves a SFDR of 34.6dB at a Nyquist input and consumes 103mW under dual supply voltages of 1.1V and 1.6V. | - |
| dc.language | eng | - |
| dc.publisher | 한국과학기술원 | - |
| dc.subject | Digital-to-analog converter (DAC)▼afour-channel time-interleaved DAC▼amaximum-overlap based phase detector▼abackground clock calibration▼ahigh speed and low power DAC | - |
| dc.subject | 디지털 아날로그 컨버터▼a4 채널 시간 인터리브 DAC▼a최대 오버랩 기반 위상 검출기▼a백그라운드 클럭 보정법▼a고속 저전력 디지탈 아날로그 컨버터 | - |
| dc.title | Time-interleaved DAC with current integration-based clock phase calibration | - |
| dc.title.alternative | 고속 동작을 위한 시간 교차 방식의 디지털 아날로그 변환기와 클럭 위상 보정법 | - |
| dc.type | Thesis(Ph.D) | - |
| dc.identifier.CNRN | 325007 | - |
| dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
| dc.contributor.alternativeauthor | 김우철 | - |
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