Time-interleaved DAC with current integration-based clock phase calibration고속 동작을 위한 시간 교차 방식의 디지털 아날로그 변환기와 클럭 위상 보정법

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 251
  • Download : 0
DC FieldValueLanguage
dc.contributor.advisorRyu, Seung-Tak-
dc.contributor.advisor류승탁-
dc.contributor.authorKim, Woo-Cheol-
dc.date.accessioned2021-05-11T19:38:40Z-
dc.date.available2021-05-11T19:38:40Z-
dc.date.issued2019-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=871471&flag=dissertationen_US
dc.identifier.urihttp://hdl.handle.net/10203/283296-
dc.description학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2019.8,[iv, 47 p. :]-
dc.description.abstractThis paper presents a four-channel time-interleaved high-speed current-steering DAC with a proposed two-stage analog multiplexer (MUX). Optimum switching times of the cascaded MUX and the sub-DACs are guaranteed by background clock phase calibration with a proposed maximum-overlap-based phase detector. A 6b 28GS/s prototype DAC fabricated in 40nm CMOS achieves a SFDR of 34.6dB at a Nyquist input and consumes 103mW under dual supply voltages of 1.1V and 1.6V.-
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectDigital-to-analog converter (DAC)▼afour-channel time-interleaved DAC▼amaximum-overlap based phase detector▼abackground clock calibration▼ahigh speed and low power DAC-
dc.subject디지털 아날로그 컨버터▼a4 채널 시간 인터리브 DAC▼a최대 오버랩 기반 위상 검출기▼a백그라운드 클럭 보정법▼a고속 저전력 디지탈 아날로그 컨버터-
dc.titleTime-interleaved DAC with current integration-based clock phase calibration-
dc.title.alternative고속 동작을 위한 시간 교차 방식의 디지털 아날로그 변환기와 클럭 위상 보정법-
dc.typeThesis(Ph.D)-
dc.identifier.CNRN325007-
dc.description.department한국과학기술원 :전기및전자공학부,-
dc.contributor.alternativeauthor김우철-
Appears in Collection
EE-Theses_Ph.D.(박사논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0