DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Choi, Yang Kyu | - |
dc.contributor.advisor | 최양규 | - |
dc.contributor.author | Han, Joon-Kyu | - |
dc.date.accessioned | 2021-05-11T19:33:34Z | - |
dc.date.available | 2021-05-11T19:33:34Z | - |
dc.date.issued | 2019 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=875348&flag=dissertation | en_US |
dc.identifier.uri | http://hdl.handle.net/10203/283054 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학부, 2019.8,[iii, 36 p. :] | - |
dc.description.abstract | In a hardware-based neuromorphic system, neurons integrate the current signals from previous synap-ses, and deliver spike-shaped voltage signals to the next synapse when the signal exceeds a certain threshold. Among diverse neuron models, leaky integrate-and-fire (LIF) model is considered to be the most suitable model for the hardware-based neuromorphic system. While synapses in neuromorphic system have been scaled in terms of area and energy as the form of memristor or unit device, LIF neurons are mostly based on the complex circuit consisting of more than 16 transistors and 3 capacitors, which makes limitations in terms of density ($> 20000 F^2$) and energy consumption (> 1000 pJ/spike). In this work, a single transistor LIF neu-ron is studied by using conventional silicon based MOSFET with $6F^2$ of footprint. The spiking property of LIF neuron is achieved only with a single transistor by using the single transistor latch (STL) phenomenon in bipolar junction transistor (BJT) operation. The LIF neuron operation is shown in both planar and vertical structured MOSFET. As well as the higher device density and lower energy consumption compared to the circuit-based LIF neuron, the proposed single transistor LIF neuron has diverse advantages compared to the previously reported high density LIF neurons, i.e., controllable neuron property, less disturbance with adja-cent neurons, and easy co-integration with silicon based synapse devices. The behavior of a single transistor neuron is analyzed depending on the dimension and applied bias to suggest the design and operation guide-line of the single transistor neuron. In addition, reliability studies are performed in terms of endurance, tem-perature and the operation stability. | - |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.subject | neuromorphic system▼aLIF neuron▼asingle transistor latch (STL) | - |
dc.subject | 뉴로모픽 시스템 | - |
dc.subject | LIF 뉴런 | - |
dc.subject | 단일 트랜지스터 래치 (STL) | - |
dc.title | (A) study of single transistor neuron for a neuromorphic system | - |
dc.title.alternative | 뉴로모픽 시스템에서 뉴런 동작이 가능한 단일 트랜지스터에 관한 연구 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 325007 | - |
dc.description.department | 한국과학기술원 :전기및전자공학부, | - |
dc.contributor.alternativeauthor | 한준규 | - |
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