A 24-30 GHz 31.7% Fractional Bandwidth Power Amplifier With an Adaptive Capacitance Linearizer

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A two-stage 24–30 GHz wideband power amplifier (PA) with an adaptive capacitance linearizer is presented, which is fabricated using a 28-nm bulk CMOS process. Staggered input gain matchings of the driver and power stages are implemented with wideband output power matchings to achieve wideband power characteristics. An adaptive capacitance linearizer is introduced at the power stage input to improve the AM-PM linearity with respect to input powers. At 24/26/28/30 GHz, it achieves 19.7/20.3/20/20 dBm Psat, 18.2/18.2/17.8/17.2 dBm P1dB, and 34.5/33.1/30/30.3 % peak power added efficiency (PAE). The small-signal gain of 21.2 dB and the 3-dB bandwidth of 8.2 GHz are achieved. It has a core size of 0.189 mm2.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2021-04
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.68, no.4, pp.1163 - 1167

ISSN
1549-7747
DOI
10.1109/tcsii.2020.3036645
URI
http://hdl.handle.net/10203/282523
Appears in Collection
EE-Journal Papers(저널논문)
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