This article presents a power-efficient buffer-embedding successive approximation register (SAR) analog-to-digital converter (ADC) that utilizes a core power supply for the source-follower buffer, having a rail-to-rail signal swing due to the capacitive-level shifting bias scheme. Also, to implement the switched-capacitor (SC) level-shifting bias scheme without bias leakage issue, a negative boosting circuit is proposed. The boosting circuit is designed without any reliability issue, even with the use of thin-oxide transistors. For low-power applications, such as the biomedical system and CMOS image sensor, the proposed ADC incorporates a skip-reset (SR) scheme, a low-power delta-readout method. In conjunction with 8x oversampling and the power-saving SR technique that has inherent chopping capability, a prototype SAR ADC fabricated in a 180-nm CMOS technology achieves a peak 74.8-dB signal-to-noise and distortion ratio (SNDR) and an 89.1-dB spurious free dynamic range (SFDR) for a 640-kHz bandwidth (BW) with an oversampling ratio (OSR) of 8, resulting in a Schreier figure of merit (FoM) of 167.3 dB. The chip area occupies 0.192 mm(2), and the power consumption is 180.1 mu W.