This article presents a 7-bit stochastic time-to-digital converter (STDC) with dual time offset arbiters that enables linearity calibration. The dual time offset arbiter with 1-bit mode selection effectively doubles time offsets available for time-to-digital conversion with minimal increase in hardware complexity. A genetic algorithm (GA)-based linearity calibration efficiently searches a huge search space to find the optimal time offset mode selection setting and a set of arbiters that lead to minimal integrated nonlinearity (INL). The combination of dual time offset arbiters and GA-based linearity calibration enables the proposed STDC to achieve ultrafine time resolution and a good linearity simultaneously. The proposed STDC also guarantees robust performance against on-die variation and gains good scalability with process technology as the linearity calibration is performed purely in the digital domain. A test chip prototype fabricated in a 65-nm CMOS technology demonstrates 360-fs time resolution with 0.75-LSB INL at 100 MS/s. The prototype achieves the effective time resolution of 630 fs, which is 1.5 times improvement compared with the prior arts.