A 24-GHz power amplifier (PA) for 5G communication is implemented with a 65-nm bulk CMOS process, which adopts analog linearization techniques of dynamic feedback control (DFC) and an adaptive bias control (ADB). The DFC decreases feedbacks and the ADB increases a gate bias of common sources (CSs) with an increase of the input signal power so that the DFC improves gain flatness and peak efficiency, and the ADB increases high power gain, saturation power, and peak efficiency. These analog linearization techniques lower the IMD3 by improving the AM-AM and AM-phase modulation (PM) of the PA. The proposed PA shows a saturation power of 18.7 dBm, a 1-stage PA gain of 15.3 dB, and a peak PAE of 37.2% with the 24.29-GHz continuous wave signal measurement. It also shows a linear power of 12.9 dBm and a linear PAE of 14.8% with a two-tone signal measurement that has a center frequency of 24.49 GHz and a bandwidth of 80 MHz.