A low-power STT-MRAM-based mixed-mode electrocardiogram (ECG) arrhythmia monitoring SoC is proposed. The proposed SoC consists of 1-MB STT-MRAM, leakage-based delay multiply-and-accumulation (MAC) unit (LDMAC), and ECG analog front end (AFE). ResNet structure with 16 1-D convolution layers and max-pooling layers is adopted for the ECG arrhythmia detection with weight reusing and partial sum reusing scheme. A nonvolatile 1-MB STT-MRAM enables deep neural network (DNN) inference to achieve higher area efficiency, lower power consumption without external memory access. The proposed mixed-mode LDMAC consumes only 4.11-nW MAC power by reusing leakage current. The proposed SoC is fabricated in 28-nm FDSOI process with 7.29-mm2 area. It demonstrates ECG arrhythmia detection with 85.1% accuracy, which is the highest score reported, and the lowest power consumption of 1.02 μW.