An Energy-Efficient Three-Stage Amplifier Achieving a High Unity-Gain Bandwidth for Large Capacitive Loads without Using a Compensation Zero

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 98
  • Download : 0
This letter presents a high-gain energy-efficient three-stage amplifier, which employs buffering-based pole relocation and dual-path structure. The proposed design does not rely on the introduction of compensation zero and preserves the unity-gain bandwidth (GBW) of the local feedback loop (LFL). Compared to the topologies using active-zero insertion, the 3rd pole is formed with a much smaller capacitance (parasitic capacitance), enabling it to be placed at a significantly higher frequency while consuming lower power. Moreover, the parasitic pole at the main path is bypassed by using an auxiliary path. Thus, the 3rd pole can be pushed to a higher frequency more easily than the topologies using an active zero. As a result, the GBW of the LFL in the proposed work is less limited. The proposed design improves the state-of-the-art FOML by 36%, LC-FOMS by 26%, and LC-FOML by 218%, while preserving robustness of the performance.
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Issue Date
2020-12
Language
English
Article Type
Article
Citation

IEEE Solid-State Circuits Letters, v.3, pp.530 - 533

ISSN
2573-9603
DOI
10.1109/lssc.2020.3036496
URI
http://hdl.handle.net/10203/280579
Appears in Collection
BiS-Journal Papers(저널논문)EE-Journal Papers(저널논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0