CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays

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dc.contributor.authorJi, Zexiko
dc.contributor.authorJung, Wanyeongko
dc.contributor.authorWoo, Jongchanko
dc.contributor.authorSethi, Khushalko
dc.contributor.authorLu, Shih-Lienko
dc.contributor.authorChandrakasan, Anantha P.ko
dc.identifier.citationAsian Solid-State Circuits Conference 2020 (A-SSCC)-
dc.description.abstractCompression of neural networks is an effective way to satisfy the requirement of memory-constrained edge devices. We propose a novel array microarchitecture that exploits compressed neural networks with nonlinearly quantized weights and supports variable activation and compressed weight bit widths. Computation is made more efficient by accumulating all the activations multiplied by the same weight prior to multiplication. This design has been fabricated in TSMC 28nm technology. It achieves 3.4 TOPS/W with 16b activations and 16b weights (4b compressed) and 3.7 TOPS/W on the convolutional layers of AlexNet (8b activations, 4b compressed weights) with the ImageNet dataset, consuming 15.6mW at 44fps. This is comparable to state-of-the-art chip implementations, while introducing increased flexibility with a simple array structure.-
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)-
dc.titleCompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays-
dc.citation.publicationnameAsian Solid-State Circuits Conference 2020 (A-SSCC)-
dc.contributor.localauthorJung, Wanyeong-
dc.contributor.nonIdAuthorJi, Zexi-
dc.contributor.nonIdAuthorWoo, Jongchan-
dc.contributor.nonIdAuthorSethi, Khushal-
dc.contributor.nonIdAuthorLu, Shih-Lien-
dc.contributor.nonIdAuthorChandrakasan, Anantha P.-
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EE-Conference Papers(학술회의논문)
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