Memory efficient hardware accelerator for kernel support vector machine based pedestrian detection

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Pedestrian detection being a vital as well as complex problem poses a unique challenge from accuracy and complexity point of view. On-chip memory requirement is one of the key issues for sliding window based detectors. In this paper a memory efficient hardware architecture is proposed which estimates the weights from a partially stored model at runtime. It uses a simple and robust feature with histogram intersection classifier. The implementation results show 80% reduction in logic resources and 46% reduction in memory without sacrificing accuracy as compared to the state of the art hardware implementations.
Publisher
Institute of Electrical and Electronics Engineers Inc.
Issue Date
2016-10-25
Language
English
Citation

13th International SoC Design Conference, ISOCC 2016, pp.127 - 128

ISSN
2163-9612
DOI
10.1109/ISOCC.2016.7799723
URI
http://hdl.handle.net/10203/278803
Appears in Collection
EE-Conference Papers(학술회의논문)
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