Atomistic modeling and simulations on the effects of interface traps in nanoscale field effect transistors

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III-V based field effect transistors (FETs) are one of the promising candidates to replace the conventional FETs thanks to their high mobility and the possibility of hetero-junction engineering. However, III-V materials are known to show significant defect concentrations at the interface with oxides. In ever-shrinking nanoscale devices, even a single interface trap may affect the device performance. It is therefore critical to accurately assess the trap effects, and for that, the first principles based atomistic approach is absolutely necessary. In this work we present a recently developed efficient computational scheme to carry out fully atomistic, fully quantum-mechanical simulations of the devices consisting of hundreds of thousands of atoms. The electron-phonon scattering effects are also included. A salient aspect of our modeling is that the trap Hamiltonian is extracted from the first-principle calculation and treated as an integral part of the device, in contrast to the existing practices that the trap is empirically modeled or post-processed independently of the electron transport in the channel. Numerical aspects to handle large sized matrices and the parallel computing scheme will be also discussed.
Publisher
한국과학기술정보연구원
Issue Date
2020-09-23
Language
English
Citation

2020 한국 슈퍼컴퓨팅 컨퍼런스

URI
http://hdl.handle.net/10203/278663
Appears in Collection
EE-Conference Papers(학술회의논문)
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