DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, Dong-Ryeol | ko |
dc.contributor.author | Moon, Kyoung-jun | ko |
dc.contributor.author | Lim, Won-mook | ko |
dc.contributor.author | Kim, Yedam | ko |
dc.contributor.author | An, Eun-ji | ko |
dc.contributor.author | Ryu, Seung-Tak | ko |
dc.date.accessioned | 2020-12-01T05:10:16Z | - |
dc.date.available | 2020-12-01T05:10:16Z | - |
dc.date.created | 2020-12-01 | - |
dc.date.created | 2020-12-01 | - |
dc.date.issued | 2020-06-10 | - |
dc.identifier.citation | Symposium on VLSI Circuits 2020 | - |
dc.identifier.uri | http://hdl.handle.net/10203/277834 | - |
dc.description.abstract | An 8b SAR-Flash ADC is proposed, where four reset-power-free complementary dynamic amplifiers (CDAs) are first engaged to a 4b loop-unrolled (LU) SAR conversion and then reutilized for a 4.5b fine interpolating-flash conversion. The hardware-reusing flash ADC not only saves power consumption and area but also reduces the number of conversion cycles. A prototype 1GS/s ADC in 28nm CMOS achieves 45.5dB SNDR at a Nyquist input with 2.55mW power consumption, leading to a FoMWalden of 16.6 fJ/c-s. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers | - |
dc.type | Conference | - |
dc.identifier.wosid | 000621657500113 | - |
dc.identifier.scopusid | 2-s2.0-85090195665 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | Symposium on VLSI Circuits 2020 | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | Virtual | - |
dc.identifier.doi | 10.1109/VLSICircuits18222.2020.9163064 | - |
dc.contributor.localauthor | Ryu, Seung-Tak | - |
dc.contributor.nonIdAuthor | Moon, Kyoung-jun | - |
dc.contributor.nonIdAuthor | Lim, Won-mook | - |
dc.contributor.nonIdAuthor | Kim, Yedam | - |
dc.contributor.nonIdAuthor | An, Eun-ji | - |
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