Pre-layout clock tree estimation and optimization using artificial neural network

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Clock tree synthesis (CTS) takes place in a very late design stage, so most of the time, power consumption is analyzed while a circuit does not contain a clock tree. We build an artificial neural network (ANN) to estimate the number of clock buffers and apply to each clock gater as well as clock source in ideal clock network. Clock structure is then constructed using such estimated clock buffers. Experiments with a few test circuits demonstrate very high accuracy of this method, average clock power estimation error less than 5%. The proposed method also allows us to find the possible minimum number of clock buffers with optimized clock parameters (e.g. target skew, clock transition time). The possible minimum number of buffers can be found by binary search algorithm and on each step of the algorithm, trained ANN is used to find such clock parameters for the target number of buffers. Using proposed clock parameter optimization, we found that the number of buffers in clock network can be reduced by 31%, on average.
Publisher
ACM, IEEE
Issue Date
2020-08-10
Language
English
Citation

ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED 2020, pp.193 - 198

DOI
10.1145/3370748.3406584
URI
http://hdl.handle.net/10203/277816
Appears in Collection
EE-Conference Papers(학술회의논문)
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