A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 32
  • Download : 0
This paper presents a high-gain energy-efficient three-stage amplifier which employs buffering-based pole relocation and a dual-path structure (BPR-DP). The proposed design does not rely on the introduction of compensation zero and preserves the unity-gain bandwidth of the local feedback loop (LFL), thus improving FOML by 1.36 times, LC-FOMS by 1.26 times, and LC-FOML by 3.18 times, as well as the performance robustness, compared to the state-of-the-art designs.
Publisher
IEEE
Issue Date
2020-06
Language
English
Citation

2020 IEEE Symposium on VLSI Circuits

DOI
10.1109/vlsicircuits18222.2020.9162960
URI
http://hdl.handle.net/10203/277732
Appears in Collection
EE-Conference Papers(학술회의논문)BiS-Conference Papers(학술회의논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0