A 0.0046mm2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero

Abstract

This paper presents a high-gain energy-efficient three-stage amplifier which employs buffering-based pole relocation and a dual-path structure (BPR-DP). The proposed design does not rely on the introduction of compensation zero and preserves the unity-gain bandwidth of the local feedback loop (LFL), thus improving FOML by 1.36 times, LC-FOMS by 1.26 times, and LC-FOML by 3.18 times, as well as the performance robustness, compared to the state-of-the-art designs.