DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Ji-Hoon | ko |
dc.contributor.author | Lee, Juhyoung | ko |
dc.contributor.author | Lee, Jinsu | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.contributor.author | Kim, Joo-Young | ko |
dc.date.accessioned | 2020-10-22T08:56:03Z | - |
dc.date.available | 2020-10-22T08:56:03Z | - |
dc.date.created | 2020-10-12 | - |
dc.date.created | 2020-10-12 | - |
dc.date.created | 2020-10-12 | - |
dc.date.issued | 2020-06-16 | - |
dc.identifier.citation | 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 | - |
dc.identifier.uri | http://hdl.handle.net/10203/276899 | - |
dc.description.abstract | This paper presents Z-PIM, an energy-efficient processing-in-memory (PIM) architecture that supports zero-skipping operations and fully-variable weight bit-precision for efficient deep neural network (DNN). The 8T-SRAM cell based bit-serial operation with hierarchical bit-line structure enables variable weight precision and reduces bit-line switching by 95.42% in convolution layers of VGG-16. Z-PIM handles abundant zeros in weight data by skip-reading their corresponding input data while read-sequence rearranging and pipelining improves throughput by 66.1%. In addition, diagonal accumulation logic is proposed to accumulate both partial-sums for bit-serial operation and spatial products. As a result, the Z-PIM chip fabricated in a 65nm process consumes average 5.294mW power and achieves 0.31-49.12 TOPS/W energy efficiency for convolution operations as sparsity and weight bit-precision vary from 0.1 to 0.9 and 1b to 16b, respectively. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Z-PIM: An Energy-Efficient Sparsity Aware Processing-In-Memory Architecture with Fully-Variable Weight Precision | - |
dc.type | Conference | - |
dc.identifier.wosid | 000621657500104 | - |
dc.identifier.scopusid | 2-s2.0-85090196679 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | 2020 IEEE Symposium on VLSI Circuits, VLSI Circuits 2020 | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | Hilton Hawaiian Village | - |
dc.identifier.doi | 10.1109/VLSICircuits18222.2020.9163015 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.localauthor | Kim, Joo-Young | - |
dc.contributor.nonIdAuthor | Kim, Ji-Hoon | - |
dc.contributor.nonIdAuthor | Lee, Juhyoung | - |
dc.contributor.nonIdAuthor | Lee, Jinsu | - |
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