A 490GHz 32mW Fully Integrated CMOS Receiver Adopting Dual-Locking FLL

Abstract

With growing interest in terahertz (THz) imaging, there has been an increasing demand for low-cost, low-power, and high-sensitivity THz receiver. Lately, heterodyne structures in CMOS technologies have been emerging as suitable solutions due to their advantages of low cost, high integration density, and high sensitivity. In order to take advantage of high sensitivity provided by heterodyne receivers, however, local-oscillator (LO) stabilization is essential, since the free-running oscillator with a poor phase noise [1], which is common in THz oscillators, can significantly degrade the SNR at the IF output. Because of that, reported THz receivers near and above 300GHz employ an external high-power LO source [2], [3] or a power-hungry on-chip phase-locked loop (PLL) [4], [5], which are undesirable in terms of power consumption and practicality. In addition, existing works [2], [5] do not integrate blocks for IF amplification or noise filtering and thus require additional external equipment, which also makes them impractical.