DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Jae Hwan | ko |
dc.contributor.author | Shin, Sung Won | ko |
dc.contributor.author | Lee, Tae In | ko |
dc.contributor.author | Hwang, Wan Sik | ko |
dc.contributor.author | Cho, Byung-Jin | ko |
dc.date.accessioned | 2020-09-18T04:16:04Z | - |
dc.date.available | 2020-09-18T04:16:04Z | - |
dc.date.created | 2020-08-13 | - |
dc.date.created | 2020-08-13 | - |
dc.date.created | 2020-08-13 | - |
dc.date.created | 2020-08-13 | - |
dc.date.issued | 2020-06-19 | - |
dc.identifier.citation | 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 | - |
dc.identifier.issn | 0743-1562 | - |
dc.identifier.uri | http://hdl.handle.net/10203/276209 | - |
dc.description.abstract | For the first time, a novel co-doping scheme of P and Sn into Ge substrate using an initiated CVD (iCVD) dopant-containing polymer film is successfully developed. This optimized doping process provides high carrier concentration n-type doping of 3 x 10(20) cm(-3) with a shallow junction depth of 50 nm. The enhancement of the P carrier concentration is attributed to less point defect generation during dopant injection and the strain relief effect induced by Sn co-doping with P into the Ge substrate. The Ge nMOSFETs with co-iCVD doping at the source/drain regions show lower off-state leakage current, higher on-current values, and lower contact resistivity compared to the Ge nMOSFETs with conventional ion implantation. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | High Quality N+/P Junction of Ge Substrate Prepared by initiated CVD Doping Process | - |
dc.type | Conference | - |
dc.identifier.wosid | 000668063000092 | - |
dc.identifier.scopusid | 2-s2.0-85098229618 | - |
dc.type.rims | CONF | - |
dc.citation.publicationname | 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | Honolulu | - |
dc.identifier.doi | 10.1109/VLSITechnology18217.2020.9265108 | - |
dc.contributor.localauthor | Cho, Byung-Jin | - |
dc.contributor.nonIdAuthor | Shin, Sung Won | - |
dc.contributor.nonIdAuthor | Hwang, Wan Sik | - |
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