DC Field | Value | Language |
---|---|---|
dc.contributor.author | Seong, Taeho | ko |
dc.contributor.author | Lee, Yongsun | ko |
dc.contributor.author | Hwang, Chanwoong | ko |
dc.contributor.author | Lee, Jeonghyun | ko |
dc.contributor.author | Park, Hangi | ko |
dc.contributor.author | Lee, Kyuho Jason | ko |
dc.contributor.author | Choi, Jaehyouk | ko |
dc.date.accessioned | 2020-08-27T06:55:36Z | - |
dc.date.available | 2020-08-27T06:55:36Z | - |
dc.date.created | 2020-08-12 | - |
dc.date.created | 2020-08-12 | - |
dc.date.created | 2020-08-12 | - |
dc.date.issued | 2020-02-19 | - |
dc.identifier.citation | 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020, pp.270 - 272 | - |
dc.identifier.issn | 0193-6530 | - |
dc.identifier.uri | http://hdl.handle.net/10203/276002 | - |
dc.description.abstract | Despite their superiority in silicon integration, ring-oscillator-based digital PLLs (RO-DPLLs) are seldom used for mobile transceivers because they have difficulty in meeting key requirements, such as low phase noise (PN) and high-frequency resolution. Due to the dilemma of setting the optimal bandwidth, considering the ΔΣM noise and the ring DCO poor PN, conventional ΔΣM-based fractional-N RO-DPLLs are limited in their ability to achieve low PN. To address this issue, the use of a digital-to-time-converter (DTC) to cancel the quantization noise (Q-noise) has become a general trend [1]. Figure 17.3.1 shows that, using a DTC that generates τ DTCaccording to the control word of the DTC, D DCW , these DPLLs can have a wide bandwidth, thereby significantly suppressing the DCO PN. However, the problem is that any nonlinearity in the loop could cause a significant increase in fractional spurs. In practice, the DTC is the major source of this nonlinearity, so one solution is to improve its linearity by pre-distorting D DCWfor its own characteristics, f DCW , [2], but this increases the design complexity. Another method is to use a successive requantizer (SR) as a quantizer (instead of a ΔΣM) [3]. The SR can mitigate fractional spurs despite the nonlinearity of the DTC, but the DTC must have a larger dynamic range than the ΔΣM with the same order. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A-58dBc-Worst-Fractional-Spur and-234dB-FoM(jitter), 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word | - |
dc.type | Conference | - |
dc.identifier.wosid | 000570129800104 | - |
dc.identifier.scopusid | 2-s2.0-85083833363 | - |
dc.type.rims | CONF | - |
dc.citation.beginningpage | 270 | - |
dc.citation.endingpage | 272 | - |
dc.citation.publicationname | 2020 IEEE International Solid-State Circuits Conference, ISSCC 2020 | - |
dc.identifier.conferencecountry | US | - |
dc.identifier.conferencelocation | San Francisco, CA | - |
dc.identifier.doi | 10.1109/ISSCC19947.2020.9062948 | - |
dc.contributor.localauthor | Choi, Jaehyouk | - |
dc.contributor.nonIdAuthor | Seong, Taeho | - |
dc.contributor.nonIdAuthor | Lee, Yongsun | - |
dc.contributor.nonIdAuthor | Hwang, Chanwoong | - |
dc.contributor.nonIdAuthor | Lee, Jeonghyun | - |
dc.contributor.nonIdAuthor | Park, Hangi | - |
dc.contributor.nonIdAuthor | Lee, Kyuho Jason | - |
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