DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoon, Jong-Hyeok | ko |
dc.contributor.author | Kwon, Kyeongha | ko |
dc.contributor.author | Bae, Hyeon-Min | ko |
dc.date.accessioned | 2020-08-25T07:55:12Z | - |
dc.date.available | 2020-08-25T07:55:12Z | - |
dc.date.created | 2020-08-18 | - |
dc.date.created | 2020-08-18 | - |
dc.date.created | 2020-08-18 | - |
dc.date.created | 2020-08-18 | - |
dc.date.issued | 2020-08 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.8, pp.2647 - 2658 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.uri | http://hdl.handle.net/10203/275964 | - |
dc.description.abstract | This paper presents a 3.125-to-28.125 Gb/s dual-lane multi-standard parallel transceiver supporting channel-independent operation. Network equipment supports multiple data rates to encompass diversified communication standards. However, network equipment supports only a fixed number of channels at each supported data rate. This lack of flexibility limits the utilization rate of the network equipment. This study proposes a clock and data recovery (CDR) IC to obtain utilization flexibility and scalability in each channel with complete channel independency. The CDR IC achieves a wide tuning capability for data rates ranging from 3.125 to 28.125 Gb/s with low clock jitter owing to the use of injection-locked oscillators in each channel. Each CDR lane generates a channel-independent injection clock signal with a fixed-frequency global clock signal using a variable clock divider and a phase rotator with the proposed harmonic distortion compensator. In addition, a frequency tracking loop is proposed using a bang-bang phase detector-based natural frequency detector to align the natural frequency of the injection-locked oscillator with the input data rate, thereby suppressing the injection spur. The test chip fabricated in a 40 nm CMOS exhibits a power efficiency of 4.72 mW/Gb/s, while generating a recovered clock jitter of 976 fs(rms) at a data rate of 25.78125 Gb/s. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | 3.125-to-28.125 Gb/s 4.72 mW/Gb/s Multi- Standard Parallel Transceiver Supporting Channel-Independent Operation in 40-nm CMOS | - |
dc.type | Article | - |
dc.identifier.wosid | 000554901800012 | - |
dc.identifier.scopusid | 2-s2.0-85089916003 | - |
dc.type.rims | ART | - |
dc.citation.volume | 67 | - |
dc.citation.issue | 8 | - |
dc.citation.beginningpage | 2647 | - |
dc.citation.endingpage | 2658 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.identifier.doi | 10.1109/TCSI.2020.2980139 | - |
dc.contributor.localauthor | Kwon, Kyeongha | - |
dc.contributor.localauthor | Bae, Hyeon-Min | - |
dc.contributor.nonIdAuthor | Yoon, Jong-Hyeok | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Clocks | - |
dc.subject.keywordAuthor | Integrated circuits | - |
dc.subject.keywordAuthor | Transceivers | - |
dc.subject.keywordAuthor | Standards | - |
dc.subject.keywordAuthor | Jitter | - |
dc.subject.keywordAuthor | Voltage-controlled oscillators | - |
dc.subject.keywordAuthor | Frequency conversion | - |
dc.subject.keywordAuthor | Channel-independent operation | - |
dc.subject.keywordAuthor | clock and data recovery | - |
dc.subject.keywordAuthor | clock flexibility | - |
dc.subject.keywordAuthor | Ethernet transceiver | - |
dc.subject.keywordAuthor | frequency tracking loop | - |
dc.subject.keywordAuthor | harmonic distortion compensator | - |
dc.subject.keywordAuthor | injection-locked loop | - |
dc.subject.keywordAuthor | multi-standard transceiver | - |
dc.subject.keywordAuthor | natural frequency detector | - |
dc.subject.keywordAuthor | parallel transceiver | - |
dc.subject.keywordAuthor | phase rotator | - |
dc.subject.keywordPlus | DATA RECOVERY CIRCUIT | - |
dc.subject.keywordPlus | CONTINUOUS-RATE CLOCK | - |
dc.subject.keywordPlus | GBPS | - |
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