A BGR-Recursive Low-Dropout Regulator Achieving High PSR in the Low- to Mid-Frequency Range

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This article proposes a bandgap reference (BGR) recursive low-dropout (LDO) regulator chip that achieves a high power supply rejection (PSR) in the low- to mid-frequency range. The presented LDO design enables the total PSR of LDO to be free from the finite ripple-rejection of the BGR circuit, resulting in low design complexity and low power consumption. To improve the PSR further, the gate buffer is modified to provide an additional ripple feedforward cancellation. The modified gate buffer also offers fast transient response and stable operation. Moreover, a light-load stabilizer loop is also suggested to provide high stability over all load conditions. A prototype chip able to supply up to 300 mA output current was implemented by 0.5-mu m 5-V CMOS devices. The PSR was measured to be -102 to -80 dB at frequencies from 100 Hz to 0.1 MHz, which is higher than that of prior LDOs with C-OUT >= 1 mu F. The proposed LDO consumes only 50 mu A at a load current of 300 mA, and a peak current efficiency of 99.98% was achieved. The line and load regulations were measured as 0.003%/V and 0.28%/A, respectively. This chip shows a figure-of-merit of 11 ps in the transient response.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2020-12
Language
English
Article Type
Article
Citation

IEEE TRANSACTIONS ON POWER ELECTRONICS, v.35, no.12, pp.13441 - 13454

ISSN
0885-8993
DOI
10.1109/tpel.2020.2996771
URI
http://hdl.handle.net/10203/275932
Appears in Collection
EE-Journal Papers(저널논문)
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