DC Field | Value | Language |
---|---|---|
dc.contributor.author | Qureshi, Muhammad Avais | ko |
dc.contributor.author | Park, Jungwoo | ko |
dc.contributor.author | Kim, Soontae | ko |
dc.date.accessioned | 2020-07-21T08:55:09Z | - |
dc.date.available | 2020-07-21T08:55:09Z | - |
dc.date.created | 2020-07-15 | - |
dc.date.created | 2020-07-15 | - |
dc.date.created | 2020-07-15 | - |
dc.date.issued | 2020-06 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.28, no.6, pp.1357 - 1370 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/275582 | - |
dc.description.abstract | Spin-transfer torque RAM (STT-RAM) is a future technology for ON-chip caches. However, it suffers from high read and write error rates. Concurrently dealing with these errors is quite challenging and incurs large performance overhead. This article proposes a smartly allocating low-cost many-bit ECC (SALE) scheme, which makes use of the low-cost many-bit error correction coding (ECC) to overcome this performance overhead. The low-cost many-bit ECC can fix many errors with low logic complexity and latency overheads. However, it requires a large number of parity bits. Therefore, SALE smartly uses low-cost many-bit ECC for only a certain type of cache lines and manages the corresponding large number of parity bits in the data array. SALE also introduces an ECC-free partition to reduce the ECC storage requirement for the STT-RAM caches. The cache lines belonging to an ECC-free partition do not have dedicated storage space for the ECC parity bits, thereby reducing the ECC storage requirement for the STT-RAM caches. Our experimental results demonstrate that SALE achieves performance close to that of an error-free cache by improving performance by 13% (16%) over the baseline scheme in single-core (quad-core) systems while requiring 50% less storage space for the ECC parity bits. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches | - |
dc.type | Article | - |
dc.identifier.wosid | 000542929200002 | - |
dc.identifier.scopusid | 2-s2.0-85085945244 | - |
dc.type.rims | ART | - |
dc.citation.volume | 28 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 1357 | - |
dc.citation.endingpage | 1370 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2020.2977131 | - |
dc.contributor.localauthor | Kim, Soontae | - |
dc.description.isOpenAccess | N | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Error correction codes | - |
dc.subject.keywordAuthor | Magnetic tunneling | - |
dc.subject.keywordAuthor | Switches | - |
dc.subject.keywordAuthor | Random access memory | - |
dc.subject.keywordAuthor | Reliability | - |
dc.subject.keywordAuthor | System-on-chip | - |
dc.subject.keywordAuthor | Writing | - |
dc.subject.keywordAuthor | False-sensing (FS) errors | - |
dc.subject.keywordAuthor | orthogonal Latin square codes (OLSC) | - |
dc.subject.keywordAuthor | read disturbance (RD) errors | - |
dc.subject.keywordAuthor | spin-transfer torque RAM (STT-RAM) | - |
dc.subject.keywordAuthor | write errors | - |
dc.subject.keywordPlus | SENSING CIRCUIT | - |
dc.subject.keywordPlus | RELIABILITY | - |
dc.subject.keywordPlus | AREA | - |
dc.subject.keywordPlus | PROTECTION | - |
dc.subject.keywordPlus | DESIGN | - |
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