THE VERTICAL-TYPE GATELESS AND CAPACITORLESS DRAM CELL BASED ON GERMANIUM AND THE METHOD FOR MANUFACTURING THEREOF저메늄 기반 수직형 게이트리스 및 커패시터리스 디램 셀 및 그 제조 방법
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choi, Yang-Kyu | ko |
| dc.contributor.author | BAE, Hagyoul | ko |
| dc.contributor.author | PARK, Jun-Young | ko |
| dc.date.accessioned | 2020-07-03T07:21:00Z | - |
| dc.date.available | 2020-07-03T07:21:00Z | - |
| dc.identifier.uri | http://hdl.handle.net/10203/275218 | - |
| dc.description.abstract | A vertical-type two-terminal biristor based on germanium improving memory performance and a method for manufacturing thereof are provided. When comparing with a three-terminal device, it is possible to increase integration because there is no gate and capacitor, and problems related to insulation degradation may be solved. Also, it may be operated at low voltage by using a germanium substrate, and problems related to leakage current may be solved because semiconductor layers having different doping concentrations are included. Also, it may protect semiconductor layers by depositing ACL (Amorphous Carbon Layer) on the semiconductor layers when wet etching. | - |
| dc.title | THE VERTICAL-TYPE GATELESS AND CAPACITORLESS DRAM CELL BASED ON GERMANIUM AND THE METHOD FOR MANUFACTURING THEREOF | - |
| dc.title.alternative | 저메늄 기반 수직형 게이트리스 및 커패시터리스 디램 셀 및 그 제조 방법 | - |
| dc.type | Patent | - |
| dc.type.rims | PAT | - |
| dc.contributor.localauthor | Choi, Yang-Kyu | - |
| dc.contributor.nonIdAuthor | PARK, Jun-Young | - |
| dc.contributor.assignee | KAIST | - |
| dc.identifier.iprsType | 특허 | - |
| dc.identifier.patentApplicationNumber | 18183260.1 | - |
| dc.identifier.patentRegistrationNumber | 3428972 | - |
| dc.date.application | 2018-07-12 | - |
| dc.date.registration | 2020-03-11 | - |
| dc.publisher.country | EI | - |
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