High Throughput and Low Cost Memory Architecture for Full Search Integer Motion Estimation in HEVC

Abstract

The two-dimensional matrix array Integer Motion Estimation (IME) architecture using Full Search Motion Estimation (FSME) algorithm for High Efficiency Video Coding (HEVC) is presented in this paper. This architecture can operate for 4K resolution video at 30 fps with latency as low as 1219 clock cycles, allowing the design working in real-time. The memory required also kept as low as 12.5kB. The proposed architecture can reach maximum frequency of 148.6 MHz using 40 nm or 195.4 MHz in 28nm Virtex-6 FPGA using Xilinx ISE version 13.1.